/ / monitoring point 1.1 answer 1. answer: 13 Analysis: 13 Byte 8KB = 8*1024 and Byte = 2 for each memory cell is 1 Byte, so the address bus is 13. 2. answer: 1KB memory has 1024 storage units. Storage units numbered from 0 to 1023. 3. answer: 1KB memory can store 1024*8 bit, 1024 Byte. 4. answer: 1GB, 1MB, 1KB are 2^30, 2^20, and 2^10 Byte. (n^m means m power n) answer: 5. address bus width of 8080, 8088, 80286, 80386 respectively is 16, 20, 24 root root root, 32 root, then their addressing capability were: 64 (KB), 1 (MB), 16 (MB), 4 (GB). 6. answer: 8080, 8088, 8086, 80286, 80386 of the data bus width of 8, 8, 16, 16, 32 root. The data they can transmit at one time are: 1 (B), 1 (B), 2 (B), 2 (B), and 4 (B). 7. answer: read 1024 bytes of data from memory, 8086 read at least 512 times, and 80386 read at least 256 times. 8. answer: in memory, data and programs are stored in binary form.
The second chapter: registers
- After reading an instruction, the value in the IP is automatically increased so that the next instruction can be read by the CPU. Current read instruction B82301
- In CPU, a programmer can read and write with instructions only registers, and programmers can control CPU by changing the contents of registers. Where the CPU executes instructions is determined by the contents of CS and IP, and the programmer can control the execution of the target instructions by changing the contents of the CS and IP.
- Mov: the transfer command cannot be used to set the values of CS and IP.
1. all registers in the general register 8086CPU are 16 bits and can store two bytes (one byte, 8 bits). The 4 memories of AX, BX, CX, and DX typically assume general data, referred to as general-purpose registers.
Snip20170529_1.png is a 16 bit register can store a 16 bit data, the maximum value is 16 times of 2 – 1 8086CPU generation in the CPU register is 8 bits, in order to ensure compatibility, AX, BX, CX, DX can be divided into 8 two bit registers used independently. AX can be divided into AH (height) and AL (low). BX can be divided into BH (height) and BL (low). CX can be divided into CH (height) and CL (low). DX can be divided into DH (height) and DL (low).
Snip20170529_3.png is stored in the register 2. words for compatible data byte 8086CPU can consider one-time treatment of two kinds of size (byte): a byte consists of 8 bit, there are 8 bit register. Word (word): a word consists of two bytes, called high byte and low byte, respectively.
, Snip20170529_2.png, ,
, Snip20170530_10.png, 3., several assembly instructions, a compilation instruction or a register name, case insensitive.
Snip20170530_4.png exercise: please calculate the table below conclusions.
Snip20170530_7.png (stuck in the third line is known in every row of the conclusions are related. (second): ax 001AH, 001AH MOV, BX is not most probably it did not actually happen.
Snip20170530_8.png) exercise: please calculate the table below conclusions.
Snip20170530_9.png built-in calculator
Snip20170530_13.png system has a binary conversion function, please combine calculation.
Snip20170601_3.png the answer is a one-dimensional linear space in the storage space under a 4. physical address of all memory elements, each memory unit has a unique address in the space (physical address). The physical address must be formed internally before the CPU issues a physical address to the address bus. 5.16 the structure of the CPU 8086CPU is a 16 bit machine (16 CPU structure) the maximum width of a computing device can handle up to 16 bit data register for access between 16 bit registers and memory for a 16 bit physical address given by 6.8086CPU 8086CPU is a 20 bit address bus, can transmit 20 bits of the address. Reach 1MB (20 1MB=1024×1024=2) 8086CPU is a 16 bit addressing capability in internal structure, one-time processing, transmission, temporary storage address is 16. From the internal structure of view: simple send only 16 bit address, showing the 64KB site capacity. 8086CPU uses a method of combining two 16 bit addresses internally to form a 20 bit physical address. The
Snip20170615_7.png address adder uses a physical address = segment address, x16+ offset address method, and combines the segment address and offset address to synthesize the physical address. For example, 8086CPU to access the address for the memory unit, 123C8H
Snip20170615_8.png process is as follows:
Snip20170615_10.png person to understand the combination of the above two maps, combined with the calculation, at first I still don’t understand, 1230×16= 12300? “WHY? Through the calculation of binary and second picture
Snip20170615_12.png to understand the figure left to four bit set above conclusion: a X binary data left 1, equivalent to X times. I am a multiplied by 2, that is 12300 suddenly know 16 is a decimal, convert 16 hex 10. Conclusion: 16 should be converted into the same number and then calculated. Conclusion: Sixteen hexadecimal segment address x16, meaning the meaning of essence of the essence of the results is to add a 0. “7. physical address = address x16+ segment offset address”: CPU in memory access, with a base address (x16 address segment) and a relative phase offset address base address, physical address given memory unit the. Segment address x16 can be considered as a base address. The 8. section of the concept of memory is not segmented, sections from CPU, because the 8086CPU with the physical address = address based (segment x16) + physical address offset address “are memory unit, we can use a piecewise way to manage memory. The offset address is 16 bits, and the addressing capability of the 16 bit address is 64K, so the maximum length of a segment is 64K.
Snip20170615_17.png to see the next 9. segment registers in the 8086CPU segment address stored in the segment register. 8086CPU has 4 segment registers: CS (code segment register), DS (data segment register), SS (stack segment register), ES (extra segment register, in front of a few do not put, put here) when the 8086CPU to access the memory by the 4 segment registers provide memory segment address. 10.CS and IP, CS, and IP are two of the most critical registers in 8086CPU that indicate the address of the current instruction that CPU is currently reading. CS is the code segment register, and the IP is the instruction pointer register. At any time 8086CPU, CPU CS:IP points to as
instructions not named xx.gif read an instruction, the value of the IP automatically increase, so that the CPU can read the next instruction. The current read instruction B82301 1. from CS:IP to the memory unit to read instructions, read the instructions into the instruction buffer; reading instruction length = IP + 2.IP, which points to the next instruction; 3. instruction execution. Go to step (1) and repeat the process. The contents of CS and IP provide the address of the CPU to execute instructions.
Snip20170617_2.png 11. CS, IP modified instructions in CPU, programmers can read and write instruction components only registers, programmers can change the contents of the register to achieve control of the CPU. Where the CPU executes instructions is determined by the contents of CS and IP, and the programmer can control the execution of the target instructions by changing the contents of the CS and IP. Mov: the transfer command cannot be used to set the values of CS and IP. Branch instruction: the instruction that can change the contents of CS and JMP: IP, one of the simplest JMP 2AE3:3 instructions that can modify CS and IP. After execution: CS=2AE3H, IP=0003H, CPU, the instruction is read from the 2AE33H. “JMP segment address: offset address” instruction function: modify the CS, offset address, modify IP with the section address given in the instruction. The function of the instruction of a JMP legal register is to modify IP with the value in the register.
Snip20170617_19.png the 1 view the CPU and memory, with more machine instructions and assembler programming steps, do not put up but strongly recommended to practice.